Ok guys , lets start off with "brushing the basics"...Am posting some questions from MIT opencourse ware..Lets try and slove them...Perhaps in the end we might build the "beta processor".. Heres the link..This assignment has no solutions..Its upto us..
http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-823-computer-system-architecture-fall-2005/assignments/psetm0.pdf
The first question as such is trivial...So lets start with the second..
ReplyDeleteOk!!! Part B) Max clock period is (Tinv+Tclk-q)max to make enable stable + max(Txormax,Enable setup)+flopsetup!!!! Guys Correct me...
ReplyDeletePart C:
tholdflop < min(txormin,tinvmin)+tclk-qmin:
tholdenable < tinvmin+tclk-qmin:
Since both holds must be met, tinvmin > tholdenable-tclk-qmin or tinvmin > tholdflop-tclk-qmin, whichever is greater.
Well what happens if these conditions are violated?? Firstly the setup is not met. In most cases set up involves a precharge or driving a node to a particular value before the clock closes.Now the node value cannot be driven..So the value at the node is unknown.The circuit ceases to operate digitally...it becomes analog :-P...u get the metastability problem here when even a small change can take the o/p to a zero or one...
In the comment,when i say setup i refer to the actions tht are done before the edge...Here the input may be stable but the precedent actions are not done
ReplyDeletePart D: There are more than one case where the circuit will fail because of skew..The obvious case is. If clock to FF0 is delayed by tclk-qmax + tinvmax + enable setup, enable would be zero at the positive tick and hence q will never be asserted on the pos edge..
ReplyDelete